An experiment was implemented to develop and train a perceptron for recognizing handwritten digits. The result of training is less than 2% of recognition errors, 17.33 Gflops performance, recognition rate of more than 10.5K characters per second at a processor core frequency of 170 MHz.
A metal detector was implemented on the basis of the X16 experimental core with a two-channel FFT unit.
A simple graphics extension with a video-controller supporting a window stack in hardware was implemented as an application-specific extension of the basic X32Carrier processor core. The video-controller assembles the image by collecting data from different window objects and determining which window data should be displayed on the screen. The graphics accelerator makes it easy to draw lines, triangular and rectangular polygons, and ellipses.
Two DE5-Net boards with StratixV chips, loaded with a 4-core processor configuration, were combined via two optical DACs into an 8-core system. 2 optical channels with a transfer rate of 2.5Gbit/sec were built using Low Latency PHY Intel/Altera IP
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