X32Carrier is a soft processor platform that can be extended with application-specific equipment organically fitting it into the basic architecture and expanding the basic set of machine instructions to obtain a target microprocessor system that is maximally adapted for solution of a specific practical task. The X32Carrier platform is a complex consisting of a set of source verilog files, memory initialization files and software designed for developing, debugging programs and monitoring the state of processor system.

X32Carrier provides the following basic service.

• a standard set of registers, including 32 128-bit general-purpose registers, 32 flag registers /each data register has its own flag register/ and 16 address registers, forming 8 pairs used to form a logical 2-component address.
• mechanism for concurrent execution of machine instructions that monitors readiness source operands in general purpose registers and the readiness of the result destination register.
• launch for execution simultaneously up to 8 machine instructions in peak and up to 4 in continuous mode.
• built-in hardware and firmware memory management system that allows you to allocate areas of memory to accommodate data and delete unnecessary ones with a single machine instruction.
• floating point arithmetic using the formats single precision (32 bits), double precision (64 bits) and extended precision (128 bits), as well as a vector of four single precision numbers or two double precision numbers packed into a 128-bit register.
• hardware support for multitasking with the execution of different programs in the time division mode, automatic context switching of registers, both basic and up to 256 64-bit custom application-specific registers.
• Built-in support for multi-core. The architecture allows the creation of a multi-core network containing up to 255 cores, each of which can have its own individual hardware expansion and instruction set extension.
• memory protection system based on two-component memory addressing [selector:offset] in which object selectors are used to find access descriptors. Object descriptors determine the privilege level of the object /4 levels are available/, its placement in the memory space, its belonging to one or a group of processes /16-bit TASK ID/ and describes possible object access modes - reading/writing and accessibility from other cores of a multi-core networks.
• support for the object segmentation mechanism, which is necessary to create in memory such objects for which there are no continuous free memory areas, but there are many small ones, the total volume of which allows create an object of the desired length.
• A convenient mechanism for passing messages between different processes running as if they were on the same core in time-division mode, and on several cores of a multi-core network. An unified mechanism for handling messages, procedure calls, and hardware interrupts. For getting messages, each process can have 2 message queues - a regular message queue and a system messages queue. Both queues are identical, but system messages are processed previously regular messages due to higher priority.
• Hardware data streams. Streams work on the FIFO principle. Designed for fast and convenient data exchange between processes running on the same core or on different cores multi-core network. The depth of each thread queue can be set individually.
• Processing violations of the object protection system and control transfer rules that occur due to incorrect operation of applications. The hardware and firmware system allows identify the cause of the error and gracefully terminate the application that caused the violation of the protection system.
• debugging software using breakpoints.

The basic equipment of the X32Carrier platform, placed inside the FPGA, includes:

• X32Carrier processor core;
• system UART running at 921600 baud;
• system timer;
• 16-channel interrupt controller;
• CRC code generator using polynomial same as in IEEE802.3;
• a 16-bit PIO register, mainly used to drive LEDs.

X32Carrier has an SPI interface for connecting SPI NOR Flash, in which the X32Kernel system software supports a simple, but quite convenient file system for storing applications and data.

Different variations of the X32Carrier can use the Avalon-MM burst interface with a width of 256 or 512 bits for connection to DDR2/DDR3 memory. There is also a variation of the X32Carrier that uses an internal FPGA block memory to form system RAM.

The X32Carrier platform software package consists of:

• "X32Kernel" kernel code that supports running and debugging applications, managing system tables and data structures, providing applications with a certain set of service functions.
• "CoreExplorer" is a Windows-based software designed to downloading software to the X32Carrier platform, downloading data, uploading data, viewing system status, its operation parameters, software debugging. CoreExplorer uses only FT232 USB-UART bridge for communication with the processor system.
• "ProcessManager" is a program that manages the compilation of software and allows you to create process files that are used by X32Kernel to expand the process in the system memory.
• "CASSM" is a configurable assembler that is the main tool for generating program code. CASSM has the ability to adjust to an individual processor instruction set. Also used for compiling the microcode of the internal blocks of the processor.
• "LLVM compiler" - used to translate the source code of programs written in C into LLVM assembler.
• "llvm2assm" - a tool for translating program from the LLVM assembler source text into the X32 base instruction set or into the previously developed X16 instruction set.

Integration of application-specific equipment into the base platform X32Carrier is carried out on the basis of a PORTAL that provides access to:

• instruction set;
• base set of GPR and flag registers;
• memory subsystem, hardware data streams and multi-core network;
• message transfer subsystem;
• context switching subsystem.

The portal contains 4 interfaces:

1. Instructions interface. This interface is used for transmission to application-specific equipment machine instructions designed to control this equipment. Transmitted along with operation codes 3 128-bit source operands selected from general purpose base registers. A 128-bit result can be returned from application-specific hardware to a general purpose register, followed by the number of the base register in which it is to be placed, arithmetic flags and bits of result size.
2. Interface to system memory. Through this interface the application-specific equipment performs accesses to the objects in main memory using logical 2-component addresses. Maximum transfer rate is 4*(Main CLOCK) Bytes/sec. The interface width is 64 bits.
3. Context interface. It provides the ability to store up to 256 64-bit values that make up context of application-specific hardware registers when the processor suspends the process and load the context of the application-specific hardware registers for the process when the processor resumes the process.
4. Message interface. When certain application-specific events occur, the hardware can send a message along with a 32-bit parameter to the desired process through this interface. The process receiving this message may be executing on this or another core in a multiprocessor network.