Hi ! I'm a single Verilog/System Verilog FPGA developer, which created MyCORES project for business and for fun too.
MyCORES is interested in integrating the developed processor cores as the basis of the target hardware. It is also very interesting to further develop and improve the technology of the base core with the added application-specific hardware.
If you are interested in the project MyCORES and you have suggestions for integrating or improving the project, please e-mail me: firstname.lastname@example.org
© 2019 MyCORES
mail to: email@example.com