Single core architecture


  1. Executive unit. It contains: a system for retrieving instructions from an instruction cache, a sequencer determining the sequence of executing instructions depending on the readiness of its operands, an integer ALU with a parallel shifter, units of multiplication, addition / subtraction, division and extraction of a square root in floating point format. Files of general-purpose registers, flags, and address registers. Address translation unit - ATU.
  2. Context controller. This is a firmware-controlled machine that is responsible for changing the context of EU registers when switching between processes, as well as performing memory allocation operations.
  3. Messenger. Firmware-controlled machine, providing interrupt processing and posting messages between processes.
  4. A system that generates multiprocessor network transaction frames.
  5. The machine responsible for routing outgoing frames and transit frames. MpMII - 32-bit media-independent interfaces.
  6. Hardware stream controller. Supports the organization of up to 255 data streams. Up to 4 streams are cached at the same time.
  7. Transaction multiplexer. Post transactions between processor units and interfaces to the memory devices.
  8. A memory buffer containing the kernel boot code and the SPI interface for connecting an external SPI Flash.
  9. SDRAM cache buffer.
  10. FFT engine. As an example of the implementation of application-specific equipment, a machine is selected that performs FFT calculation in 32-bit floating-point format. The maximum array is 2 ^ 20 values.


  The Sequencer has 10 channels along which the distribution of machine instructions from a 128-bit instruction register is made.

  1. Channel of control transfer instructions, message transfer instructions and memory allocation instructions.
  2. Integer ALU channel.
  3. Parallel shifter channel.
  4. Miscellaneous instructions channel. Those instructions performs data formatting operations.
  5. Floating point adder.
  6. Floating point multiplier.
  7. Square root calculator and floating point divider.
  8. The data transfer channel between registers and loading immediately specified constants.
  9. A channel of vectorized multiplie &accumulator. It is also used by instructions that initialize the calculation of the FFT.
  10. A channel of data exchange instructions with memory and address registers.