CoreOneV0
Single core architecture
- Executive unit. It contains: a system for retrieving instructions from an instruction cache, a sequencer determining the sequence of executing instructions depending on the readiness of its operands, an integer ALU with a parallel shifter, units of multiplication, addition / subtraction, division and extraction of a square root in floating point format. Files of general-purpose registers, flags, and address registers. Address translation unit - ATU.
- Context controller. This is a firmware-controlled machine that is responsible for changing the context of EU registers when switching between processes, as well as performing memory allocation operations.
- Messenger. Firmware-controlled machine, providing interrupt processing and posting messages between processes.
- A system that generates multiprocessor network transaction frames.
- The machine responsible for routing outgoing frames and transit frames. MpMII - 32-bit media-independent interfaces.
- Hardware stream controller. Supports the organization of up to 255 data streams. Up to 4 streams are cached at the same time.
- Transaction multiplexer. Post transactions between processor units and interfaces to the memory devices.
- A memory buffer containing the kernel boot code and the SPI interface for connecting an external SPI Flash.
- SDRAM cache buffer.
- FFT engine. As an example of the implementation of application-specific equipment, a machine is selected that performs FFT calculation in 32-bit floating-point format. The maximum array is 2 ^ 20 values.
The Sequencer has 10 channels along which the distribution of machine instructions from a 128-bit instruction register is made.
- Channel of control transfer instructions, message transfer instructions and memory allocation instructions.
- Integer ALU channel.
- Parallel shifter channel.
- Miscellaneous instructions channel. Those instructions performs data formatting operations.
- Floating point adder.
- Floating point multiplier.
- Square root calculator and floating point divider.
- The data transfer channel between registers and loading immediately specified constants.
- A channel of vectorized multiplie &accumulator. It is also used by instructions that initialize the calculation of the FFT.
- A channel of data exchange instructions with memory and address registers.