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MyCORES Design methodology

The design methodology offered by MyCORES can help you in creating your specialized processor core as well as possible adapted for use in your target applications. MyCORES provides several models of processor cores with basic instruction sets and service system functions, inside which integration of the necessary additional equipment is carried out and the addition of specialized instructions for working with the added hardware into the basic instruction set. MyCORES is a solution for deeper integration of application-specific hardware into a basic microprocessor platform.


MyCORES technology is based on a set of hardware and software tools such as:

  1. A set of MyCORES kernels (Verilog/System Verilog source code and testbenches for ModelSim software) with a basic set of machine instructions and service functions.
  2. A set of versions of system software KERNEL, adapted for different models of processors.
  3. CPUObserver - software that allows you to debug application software on the target platform. Monitor and manage the state of the target microprocessor system and manage the executable processes.
  4. Configurable assembler and translator C source to the assembler source.

Main benefits of cores

  1. 64-bit internal bus architecture, 16 128-bit general purpose registers and 16 32-bit flag registers. 16 address registers, forming 8 pairs to form a physical memory address.
  2. Competitive execution of machine instructions. The processor's hardware controls the sequence of command execution, depending on the readiness of the source operands and the result receiver for use.
  3. Some core models allow you to simultaneously send up to 8 instructions for execution on one clock cycle.
  4. The short instruction format, 16 bits, with an internal architecture of 64 bits, provides regular loading for decoding and executing up to 4 instructions per clock.
  5. The built-in memory allocation system allows you to create or release memory blocks of the desired size using a single machine instruction.
  6. Floating point arithmetic in single-precision (32-bit), double-precision (64-bit) and extended-precision (128-bit) formats.
  7. Hardware support for multiple processes execution in time-division mode.
  8. Multiprocessing. MyCORES architecture allows the construction of a two-dimensional matrix of up to 255 processors.
  9. Memory addressing by a two-component address - [selector:offset]. Selectors are used to select object descriptors by means of which the ability of a process to access an object by privilege level, by process identifier, by access mode (read / write) is checked.
  10. The message passing mechanism allows processes to exchange control information through messages. Each process can have two message queues — regular and system (it has the highest priority). These queues are filled as messages arrive in the process and are emptied as the messages are processed by the process. Like memory allocation, the transfer of a message from one process to another is activated with just one machine instruction. Messaging is possible as between processes running on the same core or on different cores in a multiprocessor system.
  11. Hardware streams. It is used for simple and convenient data transfer between processes executed on the same core or on different cores of a multiprocessor network.
  12. Multi-threaded cores with the ability to simultaneously perform 2 or more threads. Such cores have separate sets of registers for each thread, but some hardware resources are used by processes alternately.