This is the simplest, most basic architecture with 16-bit machine code. The model contains 16 128-bit general-purpose registers, 16 flag registers, 16 address registers. It has a competitive mechanism for executing instructions, which allows optimizing machine code at runtime and executing several machine instructions at the same time.
This processor core model was the result of an experiment conducted to increase the number of arithmetic instructions executed in parallel. The core is capable of performing 4 operations in a floating-point format on each clock.
The dual-thread core project is designed to increase the load of data processing units and data transmission channels by simultaneously executing two instruction flows on a single processor.
The core has a 32-bit instruction format, simplifying a series of actions for preparing address pointers and formatting data. The core also has an increased to 32 number of general purpose registers.
This processor model is a cluster of two CoreOneV0 cores. Each core has its own memory subsystem, access to which is possible from any core of the cluster bypassing FPU units.
This processor model is a cluster of four CoreOneV0 cores. Each core has its own memory subsystem, access to which is possible from any core of the cluster bypassing FPU units.
This core contains 4 independent threads with different underlying architectures. The core has 2 threads with X16 architecture and two threads X32. Kernel software can run on this processor both processes with a 16-bit and with 32-bit instruction sets.
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