The core has certain features in the EU64 block. The block contains 2 identical multiplication channels in a floating point format, 2 addition / subtraction channels in a floating point format, and 2 identical integer ALUs. The sequencer already has 13 channels for distributing instructions to various hardware resources. One of the goals of the core development was also to find out the magnitude of the decrease in the core clock frequency while increasing the instruction channels in the sequencer. The results of the experiment show the possibility of implementing hardware resources that execute any other application instructions instead of one of the duplicated multiplication, addition, or integer ALU channels.